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State encoding assigns a unique pattern of ones and zeros to each defined state of a finite-state machine (FSM). Traditionally, design criteria for FSM synthesis were speed, area or both. Following Moore's law, with technology advancement, density and speed of integrated circuits have increased exponentially. With this, power dissipation per area has inevitably increased, which has forced designers for portable computing devices and high-speed processors to consider power dissipation as a critical parameter during design consideration.〔(M. Pedram and A Abdollahi, “Low Power RT-Level Synthesis Techniques: A Tutorial” )〕〔Devadas & Malik, “A Survey of Optimization Techniques targeting Low Power VLSI Circuits”, DAC 32, 1995, pp. 242–247〕 == Background == Synthesis of FSM involves three major steps: # State minimization: As the name suggests, the number of states required to represent FSM is minimized. Various techniques and algorithms like implication tables, row matching, successive partitioning algorithm, identify and remove equivalent or redundant states. # State assignment or encoding involves choosing boolean representations of the internal states of FSM. In other words it assigns a unique binary code to each state. Selection of right encoding technique is very critical. Since wrong decision may result in FSM that uses too much logic or are is too slow or consumes more power or any combination of these. # Combinational logic minimization uses unassigned state-codes as don't-care in order to reduce the combinational logic. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「State encoding for low power」の詳細全文を読む スポンサード リンク
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